A phase locked loop (PLL) is often used for frequency synthesis. Specifically, a feedback system such as this makes it possible to multiply a reference frequency by an integer number and thus address a whole span of frequencies with a certain frequency interval. More precisely, a phase locked loop is a feedback control system which generates a frequency that is N times larger than the reference frequency that it receives as input, with N being an integer. Thus, the output frequency, which is given by a voltage-controlled oscillator, is divided by N, and then compared with a reference that may be provided by a quartz crystal. A charge pump, formed of two current sources, then reacts by injecting current into or withdrawing it from the integrating filter that drives the output oscillator.
In the case where the output frequency of the oscillator is an increasing function of its input voltage, the reaction of the loop is based on the following principle. The edge comparator detects the first of the two edges. If this detected edge belongs to the reference signal, the charge pump receives the order to dispatch current into the integrating filter. Specifically, in this case, the output signal, divided by N, lags behind the reference signal and it is therefore necessary to increase the voltage across the terminals of the oscillator.
Conversely, if the first edge detected is that of the output signal divided by N, then the charge pump absorbs current so that the voltage across the terminals of the oscillator drops. On the appearance of the second edge, the charge pump stops its activity while waiting for the next edge. Thus, the closer together the edges, the smaller the charge injected until the frequency of the output signal of the oscillator converges to N times the reference frequency.
Phase locked loops make it possible to synthesize frequencies with high accuracy and high stability. Their limitation stems from the fact that only the synthesis of integer multiples is possible, thereby limiting the number of frequencies that can be addressed on the basis of a single reference frequency.
To alleviate the problem of non-integer division, it is possible to use a so-called “fractional” phase locked loop for performing a succession of divisions by N and N+1. Thus, to perform a division by N+0.5, we divide once by N, once by N+1 and so on and so forth. The integrating filter of the loop then averages the value of the voltage driving the output oscillator of the loop.
This type of architecture, which solves the problem of decimal part division, nevertheless raises big noise problems. Specifically, unlike the conventional phase locked loops mentioned above, in which the injections of current decrease until they become negligible in the steady state, fractional phase locked loops retain large injections of current throughout their operation, since the frequency lies between N and N+1 times the reference frequency, and since it can be compared only with integer divisions.
These repeated injections of current give rise to noise that has to be apportioned. Additionally, it is the size of the binary sequence controlling the divider by N or N+1 that will impose this apportionment.
When the sequence is minimum, the voltage of the oscillator is modulated at the frequency of communication of the dividers by N and N+1. The output spectrum of the loop then comprises two parasitic lines. Additionally, these lines may render the circuit inoperative if they do not comply with the specifications regarding the noise around the fundamental.
Moreover, when the sequence gets larger, the parasitic lines, due to the period of the sequence, tend to spread out. However, the integrating filter of the loop then has time to react, thus giving rise to a variation of the fundamental over time. Thus, for very long sequences, the parasitic lines are akin to noise apportioned about the frequency generated, on account of undesired modulation of the output frequency.
In conclusion, the choice of the cut-off frequency of the phase locked loop will be a compromise limiting the filtering of the parasitic lines (ideally low in frequency) and that of the noise of the voltage-controlled oscillator (ideally high in frequency).
Document FR A 2 846 164 proposes the generation of a frequency signal equal to the product of a reference frequency times a real number by means of two dividers and two comparison signals. The system is therefore complex. It turns out to be desirable to further optimize the noise generated.